1. Field of the Invention
The present invention is related to integrated circuit fabrication and, more particularly, to lithographic patterning integrated circuit patterns by an energy beam exposure system.
2. Background Description
U.S. Pat. No. 5,294,800, entitled "E-Beam Control Data Compaction System and Method" to Chung et al., which is incorporated herein by reference, describes a system and method wherein Integrated Circuit (IC) chip designs of unlimited size are converted into tool control information for forming design patterns on mask layers or layers of a semiconductor wafer. Large chip designs were segmented into parcels of essentially equal data volume and the parcels were processed, independently, to create tool control information, called "Numerical Control data" (NC data). After each parcel was processed, the resulting processed data was combined with data from other parcels to form an NC data file that was used to control the electron beam (E-beam) tool writing the images.
The method taught in U.S. Pat. No. 5,294,800 was adequate for most repetitive chip designs, such as arrays, provided the NC data file generated did not exceed the file system or lithography tool limits. However, non-repetitive designs, such as a logic design may have few, if any, repetitive patterns with very little hierarchy to its data structure, i.e. it may be unnested ("flat") or contain very little nesting. These non-repetitive designs are, therefore, very large and result in very large NC data files. Often NC data files from these non-repetitive designs are larger than either the data processing system converting the data or the lithography tool can handle.